Many computing systems such as personal computers, automotive and airplane control, cellular phones, digital cameras, and handheld communication devices use nonvolatile writeable memories to store either data, or code, or both. Such nonvolatile writeable memories include Electrically Erasable Programmable Read-Only Memories (EEPROMs) and flash Erasable and Electrically Programmable Read-Only Memories (flash EPROMs, or flash memories). Nonvolatility is advantageous for allowing the computing system to retain its data and code when power is removed from the computing system. Thus, if the system is turned off or if there is a power failure, there is no loss of code or data.
Nonvolatile semiconductor memory devices are fundamental building blocks in prior art computer system designs. The primary mechanism by which data is stored in nonvolatile memory is the memory cell. Typical prior memory technologies provide a maximum storage capacity of one bit, or two states, per cell. Semiconductor memory cells having more than two possible states are known in the prior art, however.
One type of prior nonvolatile semiconductor memory is the flash electrically-erasable programmable read-only memory (flash EEPROM). Prior art flash EEPROMs typically allow for the simultaneous reading of several flash cells. Further, typical prior flash EEPROMs have a storage capacity that is much greater than the amount of data that can be output at any one time. Accordingly, each output of a flash EEPROM is typically associated with an array of flash cells that is arranged into rows and columns, where each flash cell in an array is uniquely addressable. When a user provides an address, row and column decoding logic in the flash EEPROM selects the corresponding flash cell.
A typical prior flash memory cell is comprised of a single field effect transistor (FET) including a select gate, a floating gate, a source, and a drain. Information is stored in the flash cell by altering the amount of charge on the floating gate, which causes the threshold voltage (V.sub.t) of the flash cell to be varied. The typical prior art flash memory cell is in one of two possible states, being either "programmed" or "erased." FIG. 1 shows flash cell voltage distribution as a function of V.sub.t for a prior art flash device. As can be seen, the erased state and the programmed state each specify a distribution or range of V.sub.t voltages. The flash cell can theoretically possess a separate identifiable state for each electron that is added to the floating gate. Practically speaking, however, prior flash cells typically have only two possible states because of inconsistencies in flash cell structure, charge loss over time, thermal considerations and inaccuracies in sensing the charge on the floating gate that affect the ability to determine the data stored in the flash cell.
To distinguish between the two possible states, the states are separated by a separation range. According to one prior method, when a flash cell is read, the current conducted by the flash cell is compared to a current conducted by reference flash cell having a threshold voltage V.sub.t set to a predetermined reference voltage that is a voltage in the separation range. A single comparator, or sense amplifier, typically makes the comparison and outputs the result.
When a flash cell is selected for reading, a biasing voltage is applied to the select gate. Simultaneously, the same biasing voltage is applied to the select gate of the reference cell. If the flash cell is programmed, excess electrons are trapped on the floating gate, and the threshold voltage V.sub.t of flash cell has increased such that the selected flash cell conducts less drain current than the reference flash cell. The programmed state of the prior flash cell is typically indicated by a logic 0. If the prior flash cell is erased, little or no excess electrons are on the floating gate, and the flash cell conducts more drain-source current than the reference cell. The erased state of the prior flash cell is typically indicated by a logic 1.
When a flash cell has three or more possible states, the prior art sensing schemes and circuits similar to that described above typically have disadvantages. FIG. 2 shows one prior art sense amplifier 200. The prior art sense amplifier 200 is comprised of a bias circuit 202, a differential amplifier 204, and shorters 206. The differential amplifier 204 is a metal-oxide semiconductor (MOS) differential pair using a current mirror load. One disadvantage of this design is that it limits the input-high level to a value of approximately 4 volts with a Vcc of 5 volts thereby limiting the common mode rejection of the sense amplifier. While an input-high voltage of 4 volts may be adequate for a single bit per cell nonvolatile writeable memory, it is typically inadequate for multi-level-cell applications because of the limited common mode range. This differential pair typically also has poor noise rejection because of the unbalanced design in that Vcc does not couple identically to both input transistors.
Another disadvantage in the prior art sense amplifier 200 is the high bias current requirement of the differential pair of the amplifier 204, the bias current requirement typically being approximately 2.5 milliamps per sense amplifier. With a large number of sense amplifiers 200 required for a multi-level-cell application, the cumulative bias current can present power problems.
Yet another disadvantage of the prior art sense amplifier 200 is the use of shorters 206 to initialize the sense amplifier 200 in a state from which it can switch quickly between the output signal levels used by the circuit. When the shorters 206 are enabled they bias the input and output of the second stage of the differential amplifier 204 by shorting them together so that the input is biased at the trip point of the stage. This shorting is required to limit problems due to slew rate limitations of the amplifier. A disadvantage of the shorting is that the shorters 206, upon release or shorting, typically create noise spikes that feed back into the sensing circuitry. This noise can propagate through the sensing circuitry before the data gets latched and can sometimes introduce error into the latched data.